In the semiconductor industry, it is oftentimes desirable to fabricate a very large-scale integrated (VLSI) circuit which includes a one-time programmable (OTP) nonvolatile memory element that can be programmed either during wafer probing or after packaging of the semiconductor die. For example, programming of an OTP nonvolatile memory element is used to provide self-contained identification information about an individual IC die or die revision. OTP nonvolatile memory can also be used for remapping addresses of defective DRAM (dynamic random access memory) cells so that functional redundant memory cells are addressed instead. OTP nonvolatile memory may also provide hard-coded digital trimming data for precision analog elements.
There are several different methods known in the art to implement nonvolatile data storage on an IC die. In one method, metallic fuses can be selectively programmed by exceeding a certain current and thereby creating an open circuit in the fuse. This changes the resistance of the metallic fuse from an initial low-resistance to a high-programmed resistance.
In another method, antifuses are selectively programmed by applying a relatively high-programming voltage to break down a dielectric material contacted by two conductive terminals of the antifuse. This permanently changes the resistance presented by the antifuse from a high initial resistance to a low-programmed resistance. The programmed resistance obtained is typically on the order of several 1000 ohms.
In accessing the antifuse for a read operation, the programmed resistance is used, for example, to couple the input capacitance of a logic gate to a high logic level provided by a power supply, or, alternatively, to a low logic level provided by a connection to ground. The time required to charge or discharge the input capacitance of the logic gate is proportional to the product of the programmed resistance of the fuse and the input capacitance of the logic gate.
The required programming voltage of prior art fuses and antifuses to implement OTP nonvolatile memory storage is quite high (on the order of 10-12 volts) and oftentimes the high-programming voltages must be routed to other circuits in the IC which are not typically capable of withstanding such high voltages. Moreover, the introduction of high-voltage programmable fuses and antifuses into an IC die may require some redesigns and process modifications in order to avoid damage to the IC die. In some instances, extra processing steps are needed which increase the overall production cost of the IC die. In addition to requiring high-programming voltages, prior art fuses and antifuses occupy a large space on the IC die which detracts from the space were other ICs devices can be formed.
In addition to the above, a nonvolatile memory cell can be formed using a standard complementary metal oxide semiconductor (CMOS) field effect transistor (FET) utilizing a mechanism in the device wherein electrons are injected into the dielectric spacer region that abuts the patterned gate stack. Omitting the halo/extension implants will cause the FET to become underlapped, which enhances the device. Using an underlapped FET as a ‘prompt-shift device’ is disclosed, for example, in U.S. Pat. No. 6,518,614 to Breitwisch et al. and in a paper that was submitted at the MTDT 2005 conference entitled “A Novel CMOS Compatible Embedded Nonvolatile Memory with Zero Mask Adder”.
Although the prompt-shift device disclosed in the above references provides a means for programming a nonvolatile memory cell, the prior art prompt-shift devices require extremely long (on the order of about 1 to about 5 seconds) programming times.
In view of the above, there is a need for providing a prompt-shift device for use in a nonvolatile memory cell in which the programming time is less than 1 second.